System Memory Module IP Core

Use of Embedded Block RAMs or Distributed Memory

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The System Memory Module is designed to support external source programming, offering user-interface options such as AHBL and AXI for efficient instruction fetching of the microcontroller.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with AMBA 3 AHB-Lite Protocol v1.0
  • Compliant with AMBA AXI4 Protocol
  • Supports AXI4 atomic access
  • Configurable as single or dual port memory, utilizing 1 or 2 AHB-Lite or AXI4 Interfaces
  • Core memory can be implemented as EBR, Distributed RAM, or Large RAM
Lattice Propel

Block Diagram

System Memory ModuleExpand Image

Ordering Information

Available for free to use in Lattice Radiant design software.

 

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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System Memory IP Module User Guide - Lattice Propel Builder
FPGA-IPUG-02073 2.4 12/11/2025 PDF 2.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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System Memory IP Module Release Notes - Lattice Propel Builder
FPGA-RN-02065 1.4 2/10/2026 PDF 232.1 KB

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