What’s New in Propel 2026.1
Discover what’s new in Lattice Propel 2026.1, featuring enhancements that improve user experience and streamline intuitive design creation. Watch now to see how the latest updates help you build FPGA-based embedded systems faster and focus on innovation.
Date: June 26, 2026 (English) Watch Now
What’s New in Radiant 2026.1
Lattice Radiant 2026.1 is purpose-built to help designers maximize productivity for small and mid-range FPGA designs. This release turbocharges development speed and drives unparalleled usability.
Date: June 26, 2026 (English) Watch Now
FPGA‑accelerated 3D Sensing for Humanoid Robot Manipulation
This demo showcases a miniaturized 3D sensor module built on AIRY3D’s patented TDM technology, mounted on a humanoid robotic arm and interfaced with the Lattice CrossLink™-NX 40 FPGA. The FPGA offloads the majority of depth computation, reducing system load and enabling efficient operation alongside an application processor such as the NVIDIA Jetson Orin™ Nano. With a wide field of view and no occlusion, the sensor delivers accurate near‑field depth awareness. This capability opens new opportunities for robotic grasping, in‑hand manipulation, and end‑effector‑mounted perception, supporting more responsive and intelligent humanoid robotics systems.
Multi‑sensor 10GbE Aggregation for NVIDIA Holoscan Using Lattice FPGAs
This demo highlights the DA322 Holoscan Adapter from Tauro Technologies, a compact multi‑sensor aggregation platform built on a low power Lattice CertusPro™‑NX FPGA. The solution supports four MIPI CSI‑2 camera inputs and aggregates HDMI, MIPI, or GMSL data into a single 10 GbE stream for efficient sensor ingest. Using RDMA, the platform feeds synchronized, high‑bandwidth data directly into NVIDIA Orin™ or Thor™ systems for real‑time visualization. With Precision Time Protocol (IEEE 1588‑2019), flexible multi‑function I/O, and an SFP+ 10 Gbps interface, the design enables scalable, space‑efficient sensor integration for advanced edge AI and visualization applications.
Real‑time 4K30 Embedded Vision Pipeline on Lattice Avant™ FPGAs
This demo showcases a real‑time 4K30 imaging pipeline implemented on the Lattice Avant FPGA platform, highlighting a complete embedded vision workflow from sensor input through FPGA‑based ISP processing to low‑latency HDMI output. The design demonstrates how Lattice Avant enables high‑performance, modular image signal processing that can be adapted to application‑specific requirements while maintaining real‑time operation. Designed for evaluation, rapid prototyping, and scalable camera development, the solution illustrates the flexibility and performance of Lattice Avant for next‑generation embedded vision systems.
Multi‑camera Aggregation for Real‑time Edge AI on Lattice Avant™ FPGAs
This demo showcases a scalable multi‑camera aggregation architecture using a Lattice Avant‑X FPGA and NVIDIA Hololink™ technology to enable ultra‑low‑latency sensor ingest for edge AI systems. Multiple camera streams are synchronized, aggregated, and preprocessed on the FPGA before being transmitted over standard 10 G or 25 G Ethernet to NVIDIA Thor™ for real‑time AI processing. By offloading camera handling, timestamping, and data conditioning from the host, the design reduces system overhead while delivering high‑bandwidth, deterministic performance. The demo highlights an AI‑ready pipeline optimized for demanding applications such as ADAS, robotics, aerospace, defense, and industrial vision.
SLVS‑EC 3.1 Image Sensor Interface on Lattice Avant™ FPGAs
This demo showcases an SLVS‑EC 3.1 image sensor interface implemented using Macnica’s SLVS‑EC IP on Lattice Avant-G and Avant-X FPGAs. Designed to support the latest Sony SLVS‑EC image sensors, the solution enables high‑performance, low‑power image capture in a compact FPGA footprint. The design supports backward compatibility with earlier SLVS‑EC standards, flexible pixel widths, multiple lane configurations, and ECC for secure data transmission. With built‑in features such as de‑skew and byte‑to‑pixel conversion, the demo highlights how Lattice Avant FPGAs simplify system design and accelerate evaluation of next‑generation high‑resolution imaging applications.
Aurora to 10G Ethernet Protocol Conversion on Lattice Avant™ FPGAs
This demo showcases an FPGA‑based protocol conversion solution from Lattice partner A.L.S.E that bridges Aurora high‑speed serial links to standard 10G Ethernet. Targeting imaging and data acquisition systems where Aurora is commonly used for low‑latency, high‑bandwidth data transfer, the design demonstrates a scalable alternative to custom PCIe boards for PC connectivity. Using a Lattice Avant Versa kit with dual SFP+ interfaces, the solution converts Aurora traffic to 10G Ethernet, simplifying system integration while maintaining performance and flexibility across heterogeneous protocols.
Single‑Chip EtherCAT® Motor Control on Lattice FPGAs
This demo showcases an integrated EtherCAT motor control solution implemented on a single Lattice FPGA, designed for real‑time motion control nodes in industrial automation systems. The design combines cyclic EtherCAT process data exchange with a deterministic field‑oriented control (FOC) motor control subsystem, delivering high‑dynamic performance with minimal latency. An embedded RISC‑V processor manages configuration and application control, while single‑chip integration consolidates EtherCAT communication, the FOC control loop, and encoder interfaces to reduce BOM, save board space, and improve system determinism.
Low Power PQC‑enabled FPGA and TPM Platform for Secure Physical AI
This demo showcases a joint Lattice, SEALSQ, and Promwad reference board designed to accelerate development of secure physical AI and industrial control systems. The platform combines a low power Lattice FPGA acting as a Root of Trust with a SEALSQ post‑quantum cryptography (PQC)‑compliant TPM, enabling secure boot, device attestation, and ongoing cyber‑resilient monitoring. With support for TPM 2.0 PQC extensions, anti‑tamper protection, and real‑time deterministic control, the reference design provides a practical foundation for building future‑ready systems that require strong security, flexibility, and rapid prototyping.
10BASE‑T1S Network Interoperability Demo on Lattice CertusPro™‑NX
This demo presents a 10BASE‑T1S Ethernet network evaluation platform developed with Canova Tech, showcasing throughput and interoperability across a mixed‑topology network. The design integrates Canova Tech’s 10BASE‑T1S Digital Controller IP synthesized on a Lattice CertusPro‑NX FPGA, with logic boards implementing MAC functionality, data handling, and control logic. A microcontroller manages system initialization, configuration, and MAC‑PHY interaction through standard interfaces, including OPEN Alliance and Media Independent Interface (MII). Together, the solution demonstrates a practical approach for validating 10BASE‑T1S Ethernet in automotive and industrial networking environments.
Full‑Bridge PCIe® Demo with NXP Hosts and Lattice Certus™ FPGAs
This demo highlights Lattice’s full‑bridge PCIe IP implemented on a Lattice Certus FPGA and demonstrated with NXP host processors. The FPGA appears as a standard PCIe endpoint with memory‑mapped BAR space, while also acting as a bus master capable of initiating transactions back to the host. A configurable application layer and embedded RISC‑V processor showcase mailbox‑based command handling, register access, and host‑to‑flash programming and verification over PCIe. By eliminating the need for an external bridge device, the design demonstrates how a single PCIe link enables efficient, bidirectional communication and remote update capabilities in NXP‑based systems.
Dual HPM Single SCM LTPI Demo
This demo showcases a high-performance LTPI setup using a single System Control Module (SCM) connected to two Host Processor Modules (HPMs) via the Lattice MachXO3™ device. It demonstrates efficient aggregation of low-speed signals—GPIO, UART, and I2C—from the SCM to both HPMs, with real-time link status monitoring and environmental sensing. Each LTPI link operates independently, ensuring uninterrupted CPLD functionality even if one HPM disconnects.
Lattice PQC Solution for Lattice MachXO5™-NX 55TDQ and PFR Demo
This demo highlights Lattice Semiconductor’s industry-first PQC-ready secure control FPGA, the Lattice MachXO5-NX 55TDQ, showcasing a single-chip solution that integrates attestation verifier, Platform Firmware Resiliency (PFR), and LTPI capabilities. Built on the power-efficient Lattice Nexus™ platform, the demo demonstrates robust post-quantum cryptography (PQC) support compliant with CNSA 2.0 and NIST standards, including ML-KEM and ML-DSA algorithms. It emphasizes crypto-agility, secure boot, hardware root of trust, and hybrid security models—making it ideal for datacenter, industrial, and communications infrastructure applications.
MPESTI Interoperability with Nuvoton and Renesas Fanout Controller Demo
This demo showcases Lattice Semiconductor’s implementation of the Modular Peripheral Sideband Tunneling Interface (MPESTI), a single-wire communication protocol developed under the Open Compute Project (OCP). It highlights seamless interoperability between a MPESTI Initiator and multiple target devices from Nuvoton and Renesas, connected via a fanout controller on the Lattice iCE40 UltraPlus™ board. The setup supports up to 64 endpoints, enables hot-plug capability, and eliminates the need for external MUX or switches—offering a scalable, cost-efficient solution for modular data center environments.
Onboarding LTPI Demo
The Onboarding LTPI Demo showcases Lattice’s seamless Plug and Play setup for Host Processor Module (HPM) endpoints using JSON-based onboarding. It highlights how LTPI bridges hardware differences between HPM and DC-SCM modules by combining I2C, UART, and GPIO into a unified high-speed interface. The demo features dynamic metadata capture, pre-link endpoint detection via a RISC-V I2C controller, and sensor interaction through a Raspberry Pi acting as a BMC—demonstrating scalable, interoperable integration for modern data center ecosystems.
Quantum Secure Key Exchange Demo
This demo showcases the establishment of a quantum-resistant secure communication channel using post-quantum cryptography (PQC) on the Lattice MachXO5™-55TDQ FPGA. It features ML-KEM for key exchange and ML-DSA for digital signing, simulating secure boot, mutual authentication, and encrypted data exchange over I2C. The setup includes pre-provisioned public keys, protection against impersonation and replay attacks, and aligns with SPDM 1.4 standards. Designed for crypto agility, the demo highlights Lattice’s commitment to future-proof firmware security in datacenter, industrial, and communications applications.
SEC-TPM with Lattice MachXO5™-NX
The SEC-TPM Demo showcases a single-chip Root of Trust solution, integrating traditional TPM functionality with post-quantum cryptography (PQC) and Platform Firmware Resilience (PFR). Running on a RISC-V core, the demo highlights secure credential management anchored to hardware, leveraging Lattice’s RNG and crypto-agile architecture. It eliminates the need for external TPM chips, simplifying the supply chain and enabling secure remote updates—making it ideal for next-generation server security applications.
Single Chip Solution for Attestation Verifier, PFR, and LTPI Demo
This demo showcases Lattice’s unified security solution built on the Lattice MachXO5™-NX 55TDQ device, integrating attestation verifier, Platform Firmware Resilience (PFR), and LTPI capabilities into a single chip. Leveraging the Lattice Sentry™ 4.0 platform, it supports both traditional cryptography and post-quantum algorithms (ML-DSA, ML-KEM), enabling secure image authentication, key exchange, and encrypted communication. The solution is compliant with SPDM 1.2, NIST 800-193, and CNSA 2.0 standards, and offers robust connectivity via I2C, I3C, SMBus, and LTPI—delivering scalable, crypto-agile protection for modern server platforms.
SPDM 1.2 Demo
The SPDM 1.2 Demo showcases the Lattice Sentry™ 4.0 platform’s robust hardware and firmware security capabilities through cryptographic attestation. Running on the Lattice MachXO5™-NX 55TDQ device, the demo verifies device identity and firmware integrity using SPDM 1.2 commands over I2C and I3C interfaces, including LTPI channels. It highlights a modular framework designed for future security upgrades, including SPDM 1.4 and post-quantum cryptography (PQC) with ML-KEM and ML-DSA support—demonstrating Lattice’s commitment to evolving cybersecurity standards.
USB to I/O Conversion Demo
The USB to I/O Conversion Demo showcases Lattice’s high-speed USB 2.0 connectivity solution built on the Lattice CrossLinkU™-NX FPGA, enabling seamless bridging between modern computing platforms and essential peripherals like GPIO, UART, and I2C. Supporting both CDC and MCTP USB classes, the demo highlights a scalable multi-endpoint architecture that manages up to three USB devices, ensuring robust system management and protocol flexibility. Designed for multi-node environments, this modular solution empowers developers with crypto-agile control and future-ready integration across industrial, embedded, and server applications.
Industrial HMI Demo: Intelligent Operator Recognition and Control
Experience a cutting-edge industrial human-machine interface (HMI) that features advanced operator attention sensing and identification. This demo enables seamless interaction with machinery, delivering real-time insights and precise control for enhanced operational efficiency.
量子威胁——安全新时代
本次会议概述了量子威胁、应对这种威胁的后量子加密技术（PQC）的基本原理，并介绍了基于FPGA的加密敏捷解决方案。
Lattice Semiconductor: Advancing Low Power FPGA Leadership
As the low power programmable leader, Lattice is at the forefront of FPGA innovation. We're committed to delivering industry-leading low power, high-performance, small footprint solutions as a steadfast, trustworthy partner to our customers worldwide.
Lattice Nexus™ 2 FPGA Platform
What’s New in Lattice Radiant™ 2024.2
Lattice Nexus™ 2 FPGA Platform: Power and Performance Leadership Demonstration
Lattice Nexus™ 2 FPGA Platform: Boot Up Demonstration
Lattice Nexus™ 2 FPGA Platform: Edge Sensor Monitoring Demonstration
Lattice Avant™-X FPGA: SERDES Demo
Lattice Avant™-X FPGA: Power Efficiency Demo
Lattice Avant™-G FPGA: Boot Up Time Demo
Glance by Mirametrix® Demonstration: Enhancing Safety and Reducing Errors in Industrial Applications
2023 Lattice Developers Conference: Opening Keynotes
Innovative Mid-Range FPGAs: Lattice Avant™-G and Lattice Avant™-X
Lattice Drive™ Solution Stack - Accelerate Automotive Application Development
Lattice Radiant – FPGA Design Complete Tools Suite
Lattice Semiconductor: Expanding Our FPGA Leadership
Accton Technology: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
NI: Power Efficient FPGA Solutions, Lattice Avant™ Launch Event
Rockwell Automation: Power Efficient FPGA Solutions, Lattice Avant™
Lattice Ecosystem Partners Share Excitement on Lattice Avant™
Lattice Avant™ FPGA Platform: AI Processing Demo
Lattice Avant™ FPGA Platform: Performance Demo
Lattice Avant™ FPGA Platform: Power Efficiency Demo
Lattice Avant™: The Next Level of FPGA Innovation
Lattice Avant™ FPGA Platform: Taking Low Power to New Heights
Lattice Semiconductor: Keynote Address at Embedded World 2022
Interview with Lattice Semiconductor: How FPGAs Solve Today’s Technology Trend Challenges
Lattice Nexus技术平台发布
CrossLink-NX发布
CrossLink-NX：低功耗视频演示
CrossLink-NX：瞬时启动演示
莱迪思半导体：低功耗可编程器件的领先供应商
莱迪思MachXO3D：加速安全系统的开发
Lattice sensAI：加速网络边缘的低功耗AI设计
使用eARC轻松实现剧院级环绕音效
本视频介绍了HDMI 2.1 eARC的如下特性：
- 高带宽 – 37M音频，支持所有音频格式
- 简单操作电视机即可带来完整的家庭影院体验
- 经得起未来视频标准变化考验的接收器
使用ECP5构建无缝的360度环视
使用ECP5和CNN实现人脸追踪 | Lattice sensAI
使用ECP5和CNN实现人员检测 | Lattice sensAI
使用ECP5和CNN实现目标计数 | Lattice sensAI
本演示通过对苹果和橘子计数来演示对象计数。演示中的推理是使用嵌入式视觉开发套件自带的ECP5-FPGA中实现的八个卷积神经网络完成的。功耗小于1W。
使用ECP5和CNN实现的速度标志牌检测 | sensAI
用于嵌入式视觉应用的快速原型设计
了解如何通过模块化视频接口平台（VIP）方便地混用和匹配多种不同类型的I/O接口。
- 输入接口选项：HDMI、DisplayPort、Dual Sensor
- 输出接口选项：HDMI、DisplayPort、USB3-GbE
使用CrossLink实现MIPI DSI到LVDS的桥接
莱迪思半导体实时在线的计算演示示例
使用Lattice CrossLink FPGA实现360环视应用
使用Lattice Radiant软件实现可预测的设计收敛
莱迪思自主机器人演示
使用 HDMI 2.1 eARC技术简化音频互连
适用于移动相关市场的CrossLink IP
莱迪思嵌入式视觉开发套件
该模块化平台结合了CrossLink FPGA的桥接功能、ECP5的低功耗、小尺寸特性以及HDMI ASSP的高分辨率优势。了解此开发套件的规格，让我们帮助您为机器人、无人机、ADAS、智能监控和AR/VR系统实现灵活的互连和低功耗图像处理功能。
莱迪思参加Embedded World 2017大会
我们展示了适用于网络边缘领域的互连和处理解决方案。
莱迪思半导体CrossLink 4:1 CSI-2聚合器IP演示
了解更多关于莱迪思CrossLink FPGA及其全新的4:1 MIPI CSI-2摄像头聚合器桥接的信息，是无人机、AR/VR、360度摄像头以及其他汽车和工业解决方案的理想选择。
使用莱迪思半导体产品的嵌入式视觉解决方案
了解莱迪思产品如何支持网络边缘计算应用（视频处理加速）、机器视觉的传感器桥接以及机器人和无人机的立体视觉功能。
面向汽车应用的FPGA
了解FPGA如何满足现高级驾驶辅助系统（ADAS）的需求。
采用莱迪思半导体产品的机器人立体视觉应用
莱迪思CrossLink FPGA、ECP5 FPGA和HDMI ASSP共同为视频处理和交付实现了清洁高效的解决方案。
面向ADAS应用的莱迪思汽车解决方案
使用莱迪思ECP5 FPGA器件可捕获来自多个汽车摄像头的图像，将它们拼接在一起，并应用多种增强/校正功能，最后为驾驶员输出清晰图像。
采用莱迪思iCE40 FPGA的信号聚合解决方案
iCE40 UltraPlus是全球尺寸最小的FPGA，具备增强的存储器和DSP，可降低系统成本、功耗并加速产品上市进程。我们的传感器数据融合以及嵌入式RISC-V和多传感器聚合演示向您展示为什么iCE40 UltraPlus是您下一代消费电子设备的理想选择。
使用莱迪思解决方案的信号聚合应用
使用莱迪思iCE40 FPGA实现视频和音频信号聚合。
使用莱迪思iCE40 FPGA的信号聚合解决方案
iCE40 UltraPlus是全球尺寸最小的FPGA，具备增强的存储器和DSP，可降低系统成本、功耗并加速产品上市进程。我们的传感器数据融合以及嵌入式RISC-V和多传感器聚合演示向您展示为什么iCE40 UltraPlus是您下一代消费电子设备的理想选择。
莱迪思iCE40 UltraPlus优点展示
了解iCE40 UltraPlus器件，它是iCE40系列中首款支持LP和HS模式的MIPI D-PHY产品。观看视频了解更多优势，例如如何使用用于帧缓冲的集成SRAM存储器驱动一个MIPI DSI显示屏。
多个CSI-2摄像头桥接
如果摄像头的接口与应用处理器的接口不匹配，此时就需要桥接解决方案。一个常见的应用实例是多路复用或合并多个MIPI CSI-2图像传感器，并将它们合并成一个MIPI CSI-2输出。CrossLink解决方案是实现无人机、360度摄像头、运动摄像机、监控和增强现实应用中摄像头聚合功能的理想选择。
ECP5 - FPGA系列
ECP5 FPGA系列打破了FPGA密度极高、功耗很大、成本惊人的陈规。针对小尺寸、大批量的应用，莱迪思优化了ECP5架构以实现低成本、小尺寸和低功耗。这些特性使得ECP5器件非常适合用于实现可编程互连解决方案，用来辅助ASIC和ASSP。
MachXO2 - 概述
查看MachXO2产品系列的概述。了解采用小尺寸封装的MachXO2如何降低成本、降低功耗并集成系统功能。看看使用免费的设计工具、IP试用和参考设计开始基于MachXO2器件的设计是多么容易。
使用Clarity Designer添加CrossLink IP
What’s New in Lattice Radiant 2025.2
Lattice Radiant 2025.2 focuses on improvement in debugging, ease of use and designer productivity. Download Radiant now to explore more features.
What’s New in Lattice Propel 2025.2
Lattice Propel 2025.2 focuses on improved design creation and accelerated project startup. Download Propel now to explore more features.
