The Lattice LPC Bus Controller Reference Design implements a LPC host and a LPC peripheral that support the seven required LPC control signals. The design is implemented in Verilog or VHDL and Lattice design tools are used for synthesis, place and route, and simulation. The design can be targeted to multiple Lattice device families, and its small size makes it portable across different FPGA/CPLD architectures. This reference design is based on the Intel Low Pin Count Interface Specification (version 1.1).
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Block Diagram
Performance and Size
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LPC Host | |||||
| LCMXO2-1200HC-5MG132CES | Verilog | >33MHz | 50 | 99 LUTs | 1.5 |
| LCMXO2-1200HC-5MG132CES | VHDL | >33MHz | 50 | 93 LUTs | 1.5 |
| LCMXO256C-3T100C | Verilog | >33MHz | 50 | 109 LUTs | 1.5 |
| LCMXO256C-3T100C | VHDL | >33MHz | 50 | 96 LUTs | 1.5 |
| LC4256ZE-5TN100C | Verilog | >33MHz | 50 | 26 Macrocells | 1.5 |
| LC4256ZE-5TN100C | VHDL | >33MHz | 50 | 26 Macrocells | 1.5 |
| LFE3-95EA-7FN1156C | Verilog | >33MHz | 52 | 107 LUTs | 1.6 |
| LFE3-95EA-7FN1156C | VHDL | >33MHz | 52 | 109 LUTs | 1.6 |
| LFXP2-5E-5M132C | Verilog | >33 MHz | 50 | 119 LUTs | 1.6 |
| LFXP2-5E-5M132C | VHDL | >33MHz | 50 | 119 LUTs | 1.6 |
| LPC Peripheral | |||||
| LCMXO2-1200HC-5MG132CES | Verilog | >33MHz | 52 | 75 LUTs | 1.5 |
| LCMXO2-1200HC-5MG132CES | VHDL | >33MHz | 52 | 73 LUTs | 1.5 |
| LCMXO256C-3T100C | Verilog | >33MHz | 52 | 75 LUTs | 1.4 |
| LCMXO256C-3T100C | VHDL | >33MHz | 52 | 73 LUTs | 1.5 |
| LC4256ZE-5TN100C | Verilog | >33MHz | 52 | 66 Macrocells | 1.4 |
| LC4256ZE-5TN100C | VHDL | >33MHz | 52 | 66 Macrocells | 1.5 |
| LFE3-95EA-7FN1156C | Verilog | >33MHz | 52 | 96 LUTs | 1.6 |
| LFE3-95EA-7FN1156C | VHDL | >33MHz | 52 | 97 LUTs | 1.6 |
| LFXP2-5E-5M132C | Verilog | >33MHz | 52 | 90 LUTs | 1.6 |
| LFXP2-5E-5M132C | VHDL | >33MHz | 52 | 95 LUTs | 1.6 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Documentation
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