The ispClock5400D Evaluation Board includes everything the designer needs to quickly configure and evaluate the ispClock5406D in-system-programmable differential clock distribution device on a fully assembled printed-circuit board. The evaluation board can be used stand-alone to review the performance and in-system programmability of the 5400D device or as a companion board and clock source for LatticeECP3 FPGA evaluation boards:
The four-layer board supports a 48-pin QFNS package, a header for user I/O and a JTAG programming cable connector. SMA connectors are installed to provide high-signal integrity access to selected high-speed I/O signals. JTAG programming signals can be generated by using an ispDOWNLOAD® programming cable connected between the evaluation board and a PC. All user-programmable features of the ispPAC-CLK5406D can be easily configured using Lattice Semiconductor's PAC-Designer® software.
