This reference design demonstrates a RISC-V-based host controller that configures the Avant FPGA using the target SPI port in x8 DDR mode. During the target SPI x8 configuration process, the bitstream is first read from an SPI flash device and loaded into DDR memory. It is then transferred byte-by-byte through the host controller general purpose input/output (GPIO) pins to the Avant device target SPI port. Additionally, this reference design includes C source code that demonstrates the complete process of configuring the Avant device through the target SPI port.
Features
- Provide clear understanding of the Target SPI x8 configuration flow and how to configure set up Avant FPGA
- Explore Processor-Based host controller architecture that supports Avant FPGA configuration via Target SPI x8
- Access to the C code implementation that follows the Target SPI x8 configuration flow
- Provide detailed steps to run the reference design and demonstrate configuration of the Avant device through Target SPI x8
- Gain hands-on experience with configuring Avant FPGA using the provided design and tools
