This reference design provides an example of how to implement a low-speed serial control link using Differential Manchester code. It takes advantage of the on-chip PLL to oversample of the incoming serial data stream. The oversampling technique is used for this application since control links usually run at a lower speed than the data path. This, together with the characteristics of the Differential Manchester code, makes the extraction of the data and the clock information from the serial data possible.
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Performance and Size
| Tested Devices* | Language | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| LCMXO2-1200HC-6TG100CES | Verilog | rx_clk > 200 MHz | 10 + 2 | 26 LUTs | 1.4 |
| LCMXO2-1200HC-6TG100CES | VHDL | rx_clk > 200 MHz | 10 + 2 | 26 LUTs | 1.4 |
| LCMXO1200E-3T100C | Verilog | rx_clk > 200 MHz | 10 + 2 | 25 LUTs | 1.4 |
| LCMXO1200E-3T100C | VHDL | rx_clk > 200 MHz | 10 + 2 | 25 LUTs | 1.4 |
| LFXP2-5E-5FT256C | Verilog | rx_clk > 200 MHz | 10 + 2 | 26 LUTs | 1.4 |
| LFXP2-5E-5FT256C | VHDL | rx_clk > 200 MHz | 10 + 2 | 26 LUTs | 1.4 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
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