Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed. This SDRAM controller reference design, located between the SDRAM and the bus master, reduces the user's effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master.
| Device Family | Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| ECP5™ 9 | LFE5U-45F- 6MG258C |
>60MHz | 73 | 95 LUTs (Verilog Source) 89 LUTs (VHDL Source) |
4.7 |
| LatticeECP3™ 3 | LFE3-95EA- 7FN1156C |
>60MHz | 73 | 133 LUTs (Verilog Source) 150 LUTs (VHDL Source) |
4.7 |
| LatticeECP™ 4 | LFECP33E- 5F484C |
>60MHz | 73 | 137 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.7 |
| iCE40™ 10 | iCE40LP8K-CM225 | >100MHz | 130 | 227 LUTs (Verilog Source) | 4.7 |
| MachXO3L11 | LCMOX3L-4300C- 5BG256C |
>100MHz | 130 | 170 LUTs (Verilog-LSE) 172 LUTs (Verilog-Syn) |
4.7 |
| MachXO2™ 1 | LCMXO2-1200HC- 5TG144C |
>60MHz | 73 | 96 LUTs (Verilog Source) 89 LUTs (VHDL Source) |
4.7 |
| MachXO™ 2 | LCMXO256C- 3T100C |
>60MHz | 73 | 92 LUTs (Verilog Source) 86 LUTs (VHDL Source) |
4.7 |
| LatticeXP2™ 5 | LFXP2-5E- 5FT256C |
>60MHz | 73 | 154 LUTs (Verilog Source) 145 LUTs (VHDL Source) |
4.7 |
| LatticeXP™ 6 | LFXP20C- 5F484C |
>60MHz | 73 | 136 LUTs (Verilog Source) 139 LUTs (VHDL Source) |
4.7 |
| ispMACH® 4000ZE 7 | LC4256ZE- 5TN100C |
>100MHz | 73 | 84 Macrocells (Verilog Source) 84 Macrocells (VHDL Source) |
4.7 |
| ispLSI® 5000VE 8 | ispLSI5512VE- 155LB272 |
>100MHz | 73 | 84 Macrocells (Verilog Source) 84 Macrocells (VHDL Source) |
4.7 |
1. Performance and utilization characteristics are generated using LCMXO2-1200HC-5TG144C, with Lattice Diamond® 3.1 design software with LSE (Lattice Synthesis Engine).
2. Performance and utilization characteristics are generated using LCMXO256C-3T100C, with Lattice Diamond 3.1 design software with LSE.
3. Performance and utilization characteristics are generated using LFE3-95EA-7FN1156C, with Lattice Diamond 3.1 design software.
4. Performance and utilization characteristics are generated using LFECP33E-5F484C with Lattice Diamond 3.1 design software.
5. Performance and utilization characteristics are generated using LFXP2-5E-5FT256C, with Lattice Diamond 3.1 design software.
6. Performance and utilization characteristics are generated using LFXP20C-5F484C with Lattice Diamond 3.1 design software.
7. Performance and utilization characteristics are generated using LC4256ZE-5TN100C with Lattice ispLEVER® Classic 1.4 software.
8. Performance and utilization characteristics are generated using ispLSI5512VE-155LB272 with Lattice ispLEVER Classic 1.4 software.
9. Performance and utilization characteristics are generated using LFE5U-45F-6MG258C, with Lattice Diamond 3.1 design software with LSE.
10. Performance and utilization characteristics are generated using iCE40LP8K-CM225, with iCEcube2 design software.
11. Performance and utilization characteristics are generated using LCMOX3L-4300C-5BG256C, with Lattice Diamond 3.1 design software using Synplify and LSE.
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Technical Resources |
| TITLE | NUMBER | VERSION | DATE | FORMAT | SIZE | ||
|---|---|---|---|---|---|---|---|
| Select All | |||||||
| Advanced SDR SDRAM Controller - Design Documentation | FPGA-RD-02087 | 4.9 | 1/22/2021 | 1.1 MB | |||
| Advanced SDR SDRAM Controller - Source Code | RD1010 | 4.8 | 9/12/2014 | ZIP | 495.7 KB | ||
| SDR SDRAM Controller - Documentation | RD1174 | 1.1 | 3/1/2014 | 1.4 MB | |||
| SDR SDRAM Controller - Source Code | RD1174 | 1.1 | 3/1/2014 | ZIP | 2.6 MB | ||
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