This reference design provides a SD Flash Controller based on the OpenCores SD Card Mass Storage Controller design. The controller connects the SD card on one side and the WISHBONE bus on the other. All transmission and reception between the host and SD card comply with the SD Physical Layer Simplified Specification 2.0 released by the SD Card Association. This reference design is designed to work with a file system where a SD card can be recognized as a system disk.
Features
- WISHBONE host interface
- DMA
- Buffer Descriptor (BD)
- Compliant with SD Physical Layer Simplified Specification 2.0
- Supports 4-bit SD mode
- Write/read FIFO with variable size
- Internal implementation of CRC16 for data lines and CRC7 for command lines
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Block Diagram
Performance and Size
| Device Family | Tested Devices* | Performance | I/O Pins | Design Size | Revision |
|---|---|---|---|---|---|
| ECP5™ 1 | LFE5UM-85F-8MG756C | >50 MHz | 203 | 1800 LUTs (Verilog Source) | 1.4 |
| LatticeECP3™ 1 | LFE3-95EA-7FN1156C | >75 MHz | 203 | 1614 LUTs (Verilog Source) | 1.4 |
| MachXO3L™ 5 | LCMXO3L-4300C-6BG256C | >50MHz | 203 | 1834 LUTs (Verilog-LSE Source) 1605 LUTs (Verilog-SYN Source) |
4.7 |
| MachXO2™ 2 | LCMXO2-7000HC-6BG332C | >50 MHz | 203 | 1824 LUTs (Verilog Source) | 1.4 |
| MachXO™ 3 | LCMXO2280C-4FT324C | >50 MHz | 203 | 1822 LUTs | 1.4 |
1. Performance and utilization characteristics are generated using LFE3-95EA-7FN1156C with Lattice Diamond 3.1 design software.
2. Performance and utilization characteristics are generated using LCMXO2-7000HC-6BG332C with Lattice Diamond 3.1 design software with LSE (Lattice Synthesis Engine).
3. Performance and utilization characteristics are generated using LCMXO2280C-4FT324C with Lattice Diamond 3.1 design software with LSE.
4. Performance and utilization characteristics are generated using LFE5UM-85F-8MG756C with Lattice Diamond 3.1 design software with LSE.
5. Performance and utilization characteristics are generated using LCMXO3L-4300C-6BG256C with Lattice Diamond 3.1 design software with LSE and Synplify Pro®.
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
Documentation
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