This high-performance Synchronous DRAM controller has been optimized for use in Lattice's MACH family of PLDs. This SDRAM Controller is designed to interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits. The Application Note shows the user where changes can be made to support other functions. For instance, changing byte enable inputs and address inputs will change the width and size of this design. This design assumes the reader has experience implementing page mode DRAM systems.
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Block Diagram
Performance and Size
| Tested Devices* | Date | Language | Testbench | Performance | I/O Pins | Design Size |
|---|---|---|---|---|---|---|
| ispMACH4A | Jul-01 | Verilog/VHDL | Yes-Verilog | 153MHz | 59 | 57 macrocells |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.
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